Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. This paper talks about implementation of unusual clock dividers. The paper starts up with simple dividers where the clock is divided by an odd number (Divide by 3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper also covers Verilog code implementation for a non-integer divider

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The scope of this paper deals with issues regarding multiple clock designs and provides short but comprehensive information on the same. Designs involving single clock are like a walk in the park… but the real challenge comes when one has to face more than one clock. Designers are faced with problems of metastability, phase or frequency difference among the clocks involved, performing asynchronous data transfer, etc. This paper covers the issue of multiple clock domains & its problems, by starting with a simple design of a single clock FIFO and later expanding it to dual clock domain and separately detailing on the problems involving more than single clock domains. In short, this paper covers what all a designer needs to make a robust and efficient design involving multiple clock domains.

Designing can be anyone’s cup of tea … but it is surely not a bed of roses. Developing a good and robust design is what really matters and contributes to the development of design on FGPA and finally on an ASIC. Tips, tricks and ideas presented in this paper are like a small drop in the ocean of efficient designing techniques, but they surely will help designers to take the first step towards developing efficient designs. The scope of this paper is to provide designers with state machine coding styles, efficient ways of writing code, portability from FPGA to ASIC, implementation of internal memories in FPGA, design tips for multiple clock designs, clock gating, clock management, using resets efficiently, synchronous designs and problem with latches.

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